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t windie ? 1.35v ddr3l-rs sdram MT41K512M16 C 32 meg x 16 x 8 banks description the 8gb ( t wind ie ? ) 1.35v ddr3l-rs sdram is a lo w-curr ent self r efr esh v ersion, via a t csr featur e , of the 1.35v ddr3l sdram device . i t uses two m icr on 4gb ddr3l-rs sdram x16 die for essentially two r anks of 4gb ddr3l-rs sdram. u nless stated other - wise , the ddr3l-rs meets the functional and timing specifications listed in the equiv alent density ddr3l sdram data sheets . r efer to m icr ons 4gb ddr3l sdram data sheet for the specifications not included in this document. s pecifications for base par t number mt41k256m16 (monolithic) corr elate to manufactur - ing par t number MT41K512M16. featur es ? u ses two 4gb x16 m icr on die in one package ? t wo r anks (includes dual cs#, odt , cke and z q balls) ? v dd = v ddq = 1.35v (1.283C1.425v ); backwar d com- patible to 1.5v oper ation ? 1.35v center -ter minated push/pull i/o ? jedec-standar d ball-out ? lo w-pr ofile package ? t c of 0c to 95c C 0c to 85c: 8192 r efr esh cy cles in 64ms C 85c to 95c: 8192 r efr esh cy cles in 32ms ? t emper atur e-compensated self r efr esh ( t csr) mode ? v er y lo w-curr ent self r efr esh mode when t c < 45c options marking ? c onfigur ation C 32 m eg x 16 x 8 banks x 2 r anks 512m16 ? fbga package (pb-fr ee) C 96-ball fbga (10mm x 14mm x 1.2mm) r ev . e tna ? t iming C cy cle time 1 C 1.25ns @ cl = 11 (ddr3l-1600) -125 C 1.5ns @ cl = 9 (ddr3l-1333) -15e C 1.87ns @ cl = 7 (ddr3l-1066) -187e ? p o w er saving C t csr m ? o per ating temper atur e C c ommer cial (0c t c 95c) n one C i ndustr ial (-40c t c 95c) it ? r evision :e note: 1. cl = cas (read) latency . t able 1: key timing parameters speed grade data rate (mt/s) target t rcd- t rp-cl t rcd (ns) t rp (ns) cl (ns) -125 1, 2 1600 11-11-11 13.75 13.75 13.75 -15e 1 1333 9-9-9 13.5 13.5 13.5 -187e 1066 7-7-7 13.1 13.1 13.1 notes: 1. backward compatible to 1066, cl = 7 (-187e). 2. backward compatible to 1333, cl = 9 (-15e). 8gb: x16 twindie ddr3l-rs sdram description pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 1 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron t echnology , inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice. http://
table 2: addressing parameter 512 meg x 16 configuration 32 meg x 16 x 8 banks x2 ranks refresh count 8k row address 32k a[14:0] bank address 8 ba[2:0] column address 1k a[9:0] page size 1kb figur e 1: 8gb: x16 ddr3l-rs part numbers package example part number: MT41K512M16tna-125m:e 96-ball 10mm x 14mm fbga tna configuration 512 meg x 16 512m16 speed grade t ck = 1.25ns, cl = 11 t ck = 1.5ns, cl = 9 t ck = 1.87ns, cl = 7 -125 -15e -187e - configuration mt41k package speed ps revision revision :e : temperature commercial { none power saving tcsr m note: 1. not all options listed can be combined to define an of fered product. use the part catalog search on http://www .micron.com for available of ferings. fbga part marking decoder due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. microns fbga part marking decoder is available at www.micron.com/decoder . 8gb: x16 twindie ddr3l-rs sdram description pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 2 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
ball assignments and descriptions figur e 2: 96-ball fbga C x16 (t op v iew) note: 1. dark balls (with rings) designate balls that differ from the monolithic versions. 8gb: x16 twindie ddr3l-rs sdram ball assignments and descriptions pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 3 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 3: 96-ball fbga C x16 ball descriptions symbol type description a[14:13], a12/bc#, a11, a10/ap, a[9:0] input addr ess inputs: provide the row address for activ a te commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low , bank selected by ba[2:0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. address inputs are referenced to v refca . a12/bc#: when enabled in the mode register (mr), a12 is sampled during read and write commands to determine whether burst chop (on-the-fly) will be performed (high = bl8 or no burst chop, low = bc4). see truth table C command in the ddr3 sdram data sheet. ba[2:0] input bank addr ess inputs: ba[2:0] define the bank to which an activ a te, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ba[2:0] are referenced to v refca . ck, ck# input clock: ck and ck# are dif ferential clock inputs. all control and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. output data strobe (dqs, dqs#) is referenced to the crossings of ck and ck#. cke[1:0] input clock enable: cke enables (registered high) and disables (registered low) internal circuitry and clocks on the dram. the specific circuitry that is enabled/disabled is de- pendent upon the ddr3 sdram configuration and operating mode. t aking cke low provides precharge power-down and self refresh operations (all banks idle),or active power -down (row active in any bank). cke is synchronous for power - down entry and exit and for self refresh entry . cke is asynchronous for self refresh exit. input buf fers (excluding ck, ck#, cke, reset#, and odt) are disabled during power-down. input buffers (excluding cke and reset#) are disabled during self refresh. cke is referenced to v refca . cs#[1:0] input chip select: cs# enables (registered low) and disables (registered high) the command decoder . all commands are masked when cs# is registered high. cs# pro- vides for external rank selection on systems with multiple ranks. cs# is considered part of the command code. cs# is referenced to v refca . ldm input input data mask: ldm is a lower -byte, input mask signal for write data. lower -byte input data is masked when ldm is sampled high along with the input data during a write access. although the ldm ball is input-only , the ldm loading is designed to match that of the dq and dqs balls. ldm is referenced to v refdq . odt[0:1] input on-die termination: odt enables (registered high) and disables (registered low) termination resistance internal to the ddr3 sdram. when enabled in normal operation, odt is only applied to each of the following balls: dq[15:0], ldqs, ldqs#, udqs, udqs#, ldm, and udm for the x16; dq0[7:0], dqs, dqs#, dm/tdqs, and nf/tdqs# (when tdqs is enabled) for the x8; dq[3:0], dqs, dqs#, and dm for the x4. the odt input is ignored if disabled via the load mode command. odt is referenced to v refca . ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered and are referenced to v refca . 8gb: x16 twindie ddr3l-rs sdram ball assignments and descriptions pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 4 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
table 3: 96-ball fbga C x16 ball descriptions (continued) symbol type description reset# input reset: reset# is an active low cmos input referenced to v ss . the reset# input re- ceiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v dd and dc low 0.2 v ddq . reset# assertion and de-assertion are asynchronous. udm input input data mask: udm is an upper -byte input mask signal for write data. upper - byte input data is masked when udm is sampled high along with that input data during a write access. although the udm ball is input-only , the udm loading is designed to match that of the dq and dqs balls. udm is referenced to v refdq . dq[7:0] i/o data input/output: lower byte of bidirectional data bus for the x16 configuration. dq[7:0] are referenced to v refdq . dq[15:8] i/o data input/output: upper byte of bidirectional data bus for the x16 configuration. dq[15:8] are referenced to v refdq . ldqs, ldqs# i/o lower byte data str obe: output with read data. edge-aligned with read data. input with write data. center-aligned to write data. udqs, udqs# i/o upper byte data str obe: output with read data. edge-aligned with read data. input with write data. dqs is center-aligned to write data. v dd supply power supply: 1.35v, 1.283C1.45v. v ddq supply dq power supply: 1.35v, 1.283C1.45v. v refca supply reference voltage for control, command, and address: v refca must be maintained at all times (including self refresh) for proper device operation. v refdq supply reference voltage for data: v refdq must be maintained at all times (excluding self refresh) for proper device operation. v ss supply ground. v ssq supply dq ground: isolated on the device for improved noise immunity. zq[1:0] reference exter nal r efer ence ball for output drive calibration: this lower byte ball is tied to an external 240 resistor (rzq), which is tied to v ssq . nc C no connect: these balls should be left unconnected (the ball has no connection to the dram or to other balls). 8gb: x16 twindie ddr3l-rs sdram ball assignments and descriptions pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 5 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
functional description ddr3l-rs the t wind ie ddr3l-rs sdram is a high-speed, v er y lo w-curr ent self r efr esh, cmos dynamic r andom access memor y device inter nally configur ed as two 8-bank ddr3l-rs sdram devices . although each die is tested individually within the dual-die package , some t wind ie test r esults may v ar y fr om a like-die tested within a monolithic die package . the ddr3l-rs sdram uses a double data r ate ar chitectur e to achiev e high-speed op- er ation. the double data r ate ar chitectur e is an 8 n -pr efetch ar chitectur e with an inter - face designed to tr ansfer two data wor ds per clock cy cle at the i/o balls . a single r ead or wr ite access consists of a single 8 n -bit-wide , one-clock-cy cle data tr ansfer at the inter - nal dram cor e and eight corr esponding n -bit-wide , one-half-clock-cy cle data tr ansfers at the i/o balls . the differ ential data str obe (dqs, dqs#) is tr ansmitted exter nally , along with data, for use in data captur e at the ddr3l-rs sdram input r eceiv er . dqs is center -aligned with data for writes . the r ead data is tr ansmitted b y the ddr3l-rs sdram and edge- aligned to the data str obes . r ead and wr ite accesses to the ddr3l-rs sdram ar e burst or iented. a ccesses star t at a selected location and continue for a pr ogr ammed number of locations in a pr ogr am- med sequence . a ccesses begin with the r egistr ation of an a ctiv a te command, which is then follo w ed b y a read or write command. the addr ess bits r egister ed coincident with the a ctiv a te command ar e used to select the bank and r o w to be accessed. the addr ess bits (including cs n #, ba n , and a n ) r egister ed coincident with the read or write command ar e used to select the r ank, bank, and star ting column location for the burst access . this data sheet pr o vides a gener al descr iption, package dimensions , and the package ballout. r efer to the m icr on monolithic ddr3 data sheet for complete infor mation r e- garding individual die initialization, register definition, command descriptions, and die operation. 8gb: x16 twindie ddr3l-rs sdram functional description ddr3l-rs pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 6 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
functional block diagram figur e 3: functional block diagram (64 meg x 16 x 8 banks x 2 ranks) tdqs# cas# ras# we# ck ck# dq[15:0] dqs, dqs# dm/tdqs a[14:0], ba[2:0] rank 0 (32 meg x 16 x 8 banks) rank 1 (32 meg x 16 x 8 banks) cs0# cke0 odt0 zq0 cs1# cke1 odt1 zq1 8gb: x16 twindie ddr3l-rs sdram functional block diagram pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 7 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
electrical specifications absolute rating stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions outside those indicated in the device data sheet is not implied. exposure to abso- lute maximum rating conditions for extended periods may adversely affect reliability. table 4: absolute maximum dc ratings parameter symbol min max units notes v dd supply voltage relative to v ss v dd C0.4 1.975 v 1 v dd supply voltage relative to v ssq v ddq C0.4 1.975 v voltage on any ball relative to v ss v in , v out C0.4 1.975 v input leakage current any input 0v v in v dd , v ref pin 0v v in 1.1v (all other pins not under test = 0v) i i C4 4 a v ref supply leakage current v refdq = v dd /2 or v refca = v dd /2 (all other pins not under test = 0v) i vref C2 2 a 2 operating case temperature t c 0 95 c 3, 4 storage temperature t stg C55 150 c notes: 1. v dd and v ddq must be within 300mv of each other at all times, and v ref must not be greater than 0.6 v ddq . when v dd and v ddq are less than 500mv , v ref may be 300mv . 2. the minimum limit requirement is for testing purposes. the leakage current on the v ref pin should be minimal. 3. max operating case temperature. t c is measured in the center of the package (see the t emperature t est point location figure). 4. device functionality is not guaranteed if the dram device exceeds the maximum t c dur- ing operation. 8gb: x16 twindie ddr3l-rs sdram electrical specifications pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 8 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
input/output capacitance the lump capacitance v alues ar e not listed. s imulations should use actual models and not lumped capacitance . t emperatur e and thermal impedance i t is imper ativ e that the ddr3l sdram devices temper atur e specifications , sho wn in the follo wing table , be maintained in or der to ensur e the junction temper atur e is in the pr oper oper ating r ange to meet data sheet specifications . an impor tant step in main- taining the pr oper junction temper atur e is using the devices ther mal impedances cor - r ectly . ther mal impedances listed in the ther mal char acter istics table apply to the cur - r ent die r evision and packages . i ncorr ectly using ther mal impedances can pr oduce significant err ors . r ead m icr on technical note tn-00-08, ther mal a pplications , pr ior to using the v alues listed in the ther mal impedance table . f or designs that ar e expected to last sev er al y ears and r equir e the flexibility to use sev er al dram die shr inks , consider using final tar get theta v alues (r ather than existing v alues) to account for incr eased ther mal impedances fr om the die siz e r eduction. the ddr3 sdram devices safe junction temper atur e r ange can be maintained when the t c specification is not ex ceeded. i n applications wher e the devices ambient tem- perature is too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications. t able 5: thermal characteristics notes 1C3 apply to entire table parameter symbol value units notes operating temperature t c 0 to 85 c 0 to 95 c 4 notes: 1. max operating case temperature t c is measured in the center of the package, as shown below . 2. a thermal solution must be designed to ensure that the device does not exceed the maximum t c during operation. 3. device functionality is not guaranteed if the device exceeds maximum t c during operation. 4. if t c exceeds 85c, the dram must be refreshed externally at 2x refresh, which is a 3.9s interval refresh rate. the use of self refresh temperature (srt) or automatic self refresh (asr), if available, must be enabled. 8gb: x16 twindie ddr3l-rs sdram electrical specifications pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 9 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
figure 4: temperature test point location test point length (l) width (w) 0.5 (w) 0.5 (l) table 6: thermal impedance die rev package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) notes e 96-ball low con- ductivity 48.0 36.4 31.9 n/a 1.8 1 high con- ductivity 28.6 23.4 21.6 16.5 n/a note: 1. thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. 8gb: x16 twindie ddr3l-rs sdram electrical specifications pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 10 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
electrical specifications C i cdd parameters t able 7: ddr3l-rs cdd specifications and conditions (rev . e) note 8 applies to the entire table combined symbol individual die status bus width -187e -15e -125 units notes i cdd0 i cdd0 = i dd0 + i dd2p0 + 5 x16 72 75 83 ma 1 i cdd1 i cdd1 = i dd1 + i dd2p0 + 5 x16 97 101 104 ma 1 i cdd2p0 (slow exit) i cdd2p0 = i dd2p0 + i dd2p0 x16 24 24 24 ma 1 i cdd2p1 (fast exit) i cdd2p1 = i dd2p1 + i dd2p0 x16 36 38 42 ma 1 i cdd2q i cdd2q = i dd2q + i dd2p0 x16 34 36 39 ma 1 i cdd2n i cdd2n = i dd2n + i dd2p0 x16 34 36 38 ma 1 i cdd2nt i cdd2nt = i dd2nt + i dd2p0 x16 42 46 49 ma 1 i cdd3p i cdd3p = i dd3p + i dd2p0 x16 39 42 45 ma 1 i cdd3n i cdd3n = i dd3n + i dd2p0 x16 49 52 55 ma 1 i cdd4r i cdd4r = i dd4r + i dd2p0 + 5 x16 193 210 244 ma 1 i cdd4w i cdd4w = i dd4w + i dd2p0 = 5 x16 146 161 180 ma 1 i cdd5b i cdd5b = i dd5b + i dd2p0 x16 233 236 243 ma 1 room temperature i cdd6 i cdd6 = i dd6 + i dd6 x16 7.0 7.0 7.0 ma 2 45 o c i cdd6et i cdd6 = i dd6 + i dd6 x16 7.4 7.4 7.4 ma 3 elevated temperature i cdd6 i cdd6 = i dd6 + i dd6 x16 14 14 14 ma 4 17 17 17 ma 5 extended temperature i cdd6et i cdd6et = i dd6et + i dd6et x16 28 28 28 ma 6 36 36 36 ma 7 i cdd7 i cdd7 = i dd7 + i dd2p0 + 5 x16 211 230 256 ma 1 i cdd8 i cdd8 = 2 i dd2p0 + 4 x16 28 28 28 ma 1 notes: 1. t c = 85c; sr t is disabled, asr is disable. v alue is maximum. 2. room temperature; sr t is disabled, asr is enabled. v alue is typical. 3. t c 45c; sr t is disabled, asr is enabled). v alue is typical. 4. t c = 80c; sr t is disabled, asr is enabled). v alue is typical. 5. 45c < t c 80c; sr t is disabled, asr is enabled. v alue is maximum. 6. t c = 95c; sr t is disabled, asr is enabled. v alue is typical. 7. 85c < t c 95c; sr t is disabled, asr is enabled. v alue is maximum. 8. i cdd values reflect the combined current of both individual die. i dd x represents individu- al die values. 8gb: x16 twindie ddr3l-rs sdram electrical specifications C i cdd parameters pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 11 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
t emperatur e-compensated self refr esh (tcsr) the temper atur e-compensated self r efr esh ( t csr) featur e substantially r educes the self r efr esh curr ent (i dd6 ). t csr takes affect when t c is less than 45c and the auto self r e- fr esh (asr) function is enabled. asr is r equir ed to use the t csr featur e and is enabled manually via mode r egister 2 (mr2[6]). s ee m ode r egister 2 (mr2) d efinition belo w . e nabling asr also automatically changes the dram self r efr esh r ate fr om 1x to 2x when the case temper atur e ex ceeds 85c. this allo ws the user to oper ate the dram bey ond the standar d 85c limit up to the optional extended temper atur e r ange of 95c while in self r efr esh mode . when asr is disabled and t c is 0c to 85c, the self r efr esh modes r efr esh r ate is as- sumed to be at the nor mal r ate (sometimes r eferr ed to as 1x r efr esh r ate). also , if asr is disabled and t c is 85c to 95c, the user must select the sr t extended-temper atur e self r efr esh r ate (sometimes r eferr ed to as 2x r efr esh r ate). sr t is selected via mode r egister 2 (mr2[7]) r egister . s ee m ode r egister 2 (mr2) d efinition belo w . spd settings should always suppor t 05h (101 binar y) in b yte 31. mode register 2 (mr2) m ode r egister 2 (mr2) contr ols additional functions and featur es not av ailable in the other mode r egisters . the auto self r efr esh (asr) function is of par ticular inter est for the ddr3l-rs sdram because the m icr on ddr3l-rs sdram goes into t csr mode when asr has been enabled. this function is contr olled via the bits sho wn in the figur e belo w . figure 5: mode register 2 (mr2) definition m14 0 1 0 1 m15 0 0 1 1 mode register mode register set 0 (mr0) mode register set 1 (mr1) mode register set 2 (mr2) mode register set 3 (mr3) a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register 2 (mr2) address bus 9 7 6 5 4 3 8 2 1 0 a10 a12 a11 ba0 ba1 10 11 12 13 14 15 1 cwl 0 1 0 ba2 asr 16 0 1 a13 0 1 0 1 0 1 0 1 0 1 0 1 srt r tt(wr) m6 0 1 auto self refresh (optional) disabled: manual enabled: automatic m7 0 1 self refresh temperature normal (0c to 85c) extended (0c to 95c) cas write latency (cwl) 5 ck ( t ck 2.5ns) 6 ck (2.5ns > t ck 1.875ns) 7 ck (1.875ns > t ck 1.5ns) 8 ck (1.5ns > t ck 1.25ns) 9 ck (1.25ns > t ck 1.07ns) 10 ck (1.071ns > t ck 0.938ns) reserved reserved m3 0 1 0 1 0 1 0 1 m4 0 0 1 1 0 0 1 1 m5 0 0 0 0 1 1 1 1 m9 0 1 0 1 m10 0 0 1 1 dynamic odt (r tt(wr) ) r tt(wr) disabled rzq/4 rzq/2 reserved note: 1. mr2[17, 14:11, 8, and 2:0] are reserved for future use and must all be programmed to 0. 8gb: x16 twindie ddr3l-rs sdram temperature-compensated self refresh (tcsr) pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 12 micron t echnology , inc. reserves the right to change products or specifications without notice. 2012 micron technology, inc. all rights reserved.
package dimensions figur e 6: 96-ball fbga C die revision e (package code tna) seating plane 0.12 a ball a1 id (covered by sr) ball a1 id 0.25 min 1.1 0.1 6.4 ctr 10 0.1 0.8 typ 12 ctr 14 0.1 96x ?0.45 dimensions apply to solder balls post- reflow on ?0.33 nsmd ball pads. 0.8 typ 1 2 3 7 8 9 a b c d e f g h j k l m n p r t a notes: 1. all dimensions are in millimeters. 2. solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). 8gb: x16 twindie ddr3l-rs sdram package dimensions pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 13 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.
8000 s. federal w ay , p .o. box 6, boise, id 83707-0006, t el: 208-368-3900 www .micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron t echnology , inc. t windie is a trademark of micron t echnology , inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 8gb: x16 twindie ddr3l-rs sdram package dimensions pdf: 09005aef84ccb511 ddr3l-rs_8gb_x16_2cs_twindie.pdf - rev. d 05/13 en 14 micron t echnology , inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved.

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